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1
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An Expurgated Union Bound for Space-Time Code Systems
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First Author
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LNCS (Springer-Verlag), Vol. 3124
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2004
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2
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Analyzing the Performance of Mesh and Fat-Tree topologies for Network on Chip design
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First Author
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LNCS (Springer-Verlag),Vol. 3824
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2005
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3
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Designing On-Chip Network based on optimal latency criteria
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First Author
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LNCS (Springer-Verlag) Vol. 3820
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2005
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4
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The Optimum Network on Chip Architectures for Video Object Plane Decoder Desig
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First Author
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LNCS (Springer-Verlag), Vol. 4330
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2006
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5
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Throughput aware mapping for Network on Chip Design of H.264 Decoder
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First Author
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LNCS (Springer-Verlag), Vol. 4331
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2006
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6
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Realization of Video Object Plane Decoder on On-Chip-Network Architecture
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Co-Author
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LNCS (Springer-Verlag), Vol. 3820
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2005
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7
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Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling
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First Author
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LNCS (Springer-Verlag), Vol. 4742
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2007
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8
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An QoS Aware Mapping of Cores Onto NoC Architectures
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Co-Author
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LNCS (Springer-Verlag), Vol. 4742
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2007
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9
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Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip
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Co-Author
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LNCS (Springer-Verlag), Vol. 4742
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2007
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10
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Tightening union bound by applying Verdu theorem for LDPC
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First Author
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IEEE PIMRC2003
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2003
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11
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Expurgated Tangential Bound of Low Density Parity Check
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First Author
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IEEE CSNDSP2004
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2004
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12
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Expurgated Sphere Bound of LDPC
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First Author
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IEEE PIMRC2004
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2004
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13
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On Chip Network: Topology design and evaluation using NS2
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First Author
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IEEE ICACT2005
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2005
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14
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Designing Network on Chip based on Fat-Tree topology
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First Author
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IEEE ICT2005
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2005
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15
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On-Chip Network latency analysis and optimization using Branch and Bound algorithm
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First Author
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ITC-CSCC2005
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2005
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16
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Realization of Video Object Plane decoder on Mesh On Chip Network Architecture
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Co-Author
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IASTED CSS2005
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2005
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17
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Implementation of H.264 Decoder on On-Chip-Network Architecture
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Co-Author
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ISOCC2005
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2005
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18
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An optimum mapping of IPs for On-Chip Network design based on the minimum latency constraint
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First Author
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IEEE Tencon2005
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2005
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19
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The Optimized Tree-based Network on Chip Topologies for H.264 Decoder Design
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First Author
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IEEE ICCES’06
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2006
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20
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Multiplane Virtual Channel Router for Network-on-Chip Design
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Co-Author
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IEEE HUT-ICCE’06
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2006
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21
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A Virtual Channel Router with Wavefront Allocation Scheme for On-Chip Network
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Co-Author
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IEEE HUT-ICCE’06
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2006
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22
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Realizing Network on Chip Design of H.264 Decoder Based on Throughput Aware Mapping
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First Author
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IEEE HUT-ICCE’06
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2006
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23
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Assessing Routing Behavior on On-Chip-Network
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Co-Author
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IEEE ICCSC’06
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2006
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24
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High-rate Space-Time Block Coded Spatial Modulation
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Co-Author
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IEEE ATC’12
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2012
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25
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A Novel Spatially-Modulated orthogonal Space-Time Block Code For 4 Transmit Antennas
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Co-Author
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IEEE ISSPIT’ 12
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